IEI Integration ICE-DB-T6 - Manual (Page 71)

Type 6 Carrier Board Design Guide
Page 61
3.11.4 Routing Guide Line
3.11.4.1 HSYNC and VSYNC Signals
The horizontal and vertical sync signals 'VGA_HSYNC' and 'VGA_VSYNC' provided by
the COM Express module are 3.3V tolerant outputs. It is necessary to implement high
impedance unidirectional buffers since VGA monitors may drive the monitor sync signals
with 5V tolerance. These buffers avoid that VGA monitors may attempt to drive the
monitor sync signals back to the module and prevent potential electrical over-stress of the
module.
3.11.4.2 ESD
For optimal ESD protection, additional low capacitance clamp diodes should be
implemented on the monitor sync signal and DAC. Please see the reference schematic.
3.11.4.3 DDC Interface
COM Express provides a dedicated I2C bus for the VGA interface. It corresponds to the
DDC interface that is defined by VESA and is used to read out the CRT monitor specific
Extended Display Identification Data (EDID). The appropriate signals 'VGA_I2C_DAT' and
'VGA_I2C_CK' of the COM Express module are supposed to be 3.3V tolerant.
The ICE Module implements the LVDS EDID ROM on board. If customer wants to fix
the resolution or EDID information, please contact IEI for ODM Service.
3.11.5 VGA Reference Design
This reference design shows a circuitry implementing a VGA port.