IEI Integration ICE-DB-T6 - Manual (Page 66)

Type 6 Carrier Board Design Guide
Page 56
3.9.4.2 LAN Ground Plane Separation
Isolated separation between the analog ground plane and digital ground plane is
recommended. If they are not implemented properly then bad ground plane partitioning
could cause serious EMI emissions and degrade analog performance due to bouncing
noise. The plane area underneath the magnetic module should be left void. The void area
is to keep transformer induced noise away from the power and system ground planes. For
ESD protection, a 3kV high voltage capability capacitor is recommended to connect to this
chassis ground for ESD protection. The isolated ground (chassis ground) directly
connects to the fully shielded RJ-45 connector. For better isolation, it is important to
maintain a gap between chassis ground and system ground that is wider than 60mils.
Additionally, a ferrite bead can be placed parallel to the capacitor.
3.10 LPC (Low Pin Count Interface)
The Low Pin Count Interface was defined by the Intel® Corporation to facilitate the
industries transition to legacy free systems. It allows the integration of low-bandwidth
legacy I/O components in the system, which are provided by a Super I/O controller.
Furthermore, LPC can be used to interface Firmware Hubs, Trusted Platform Module
(TPM) devices and Embedded Controller solutions. Data transfer on the LPC bus is
implemented over a 4-bit serialized data interface, which uses a 33MHz LPC bus clock.
For more information about LPC bus refer to the 'Intel Low Pin Count Interface
Specification Revision 1.1'.
3.10.1 Signal Description
Since COM Express is designed to be a legacy free standard for embedded modules, it
does not support legacy functionality such as PS/2 keyboard/mouse, parallel and serial
ports. Instead, COM Express provides an LPC interface that can be used to add
peripheral devices to the carrier board design. The reduced pin count of the LPC interface
makes it easy to implement such devices. All corresponding signals can be found on the
modules connector rows A and B.