IEI Integration ICE-DB-T6 - Manual (Page 33)

Type 6 Carrier Board Design Guide
Page 23
3.1.3 PEG_ENABLE#
PEG_ENABLE# is defined on the COM Express connector as a method to configure the
COM Express PCIe lanes 16 through 32 on the C-D connector as a PCI Express Graphics
port for an external graphics device. The usual effect of pulling PEG_ENABLE# low is to
disable the on-Module graphics engine. For some modules, it is possible to configure the
module such that the internal graphics engine remains active, even when the external
PEG interface is being used for a Carrier Board graphics device. This is Module
dependent. ICE Modules implement the auto-detect function. So, please reserve this pin
for future use.
3.1.4 PCI Express Test Points and Probing
IEI follows the suggestion provided by Intel® to preserve 0-Ω on the carrier board. The
inclusion of test points and probing structures has the ability to impact the loss and jitter
budgets of a PCI Express interconnect. This is not to say that they cannot be tolerated. In
general, test points and probe structures should not introduce stubs on the differential
pairs or cause significant deviation from the recommendations given throughout this
chapter. Existing vias, pads or pins should be used wherever possible to accommodate
such structures. Careful consideration must be taken whenever additional probing
structures are used.
The PCI Express based specification requires the data eyes to be measured into a 50-Ω
resistor terminated to ground. To facilitate the measurement, an additional test structure
may be required on a test board. This test structure should not be included in a production
board because it will affect the overall signal quality and resulting margins. The three-pad
test structure consists of the footprints of two resistors, perpendicular to each other
forming a “L” shape. The resistor package/footprint should be as small as possible,
preferably 0402. To enable the test mode, a 50 Ω ±1% resistor stuffing option is needed to
break the path. This will force the transmitter port to enter the compliance mode and begin
transmitting the compliance packet. Otherwise, use a 0-Ω resistor to continue the trace
route to the Rx port. This will allow normal operation of the device.