2 pci express, Xpress, Figure 3-4: peg layout trace example – IEI Integration ICE-DB-T6 User Manual

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Type 6 Carrier Board Design Guide

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Preferred Routing

Alternative Routing

Bad Routing

Preferred Routing

Figure 3-4: PEG Layout Trace Example

3.2 PCI Express

PCI Express provides a scalable, high-speed, serial I/O point-to-point bus connection. A

PCI Express lane consists of dual simplex channels, each implemented as a low-voltage

differentially driven transmit pair and receive pair. They are used for simultaneous

transmission in each direction. The bandwidth of a PCI Express link can be scaled by

adding signal pairs to form multiple lanes between two devices. The PCI Express

specification defines x1, x4, x8, x16, and x32 link widths. Each single lane has a raw data

transfer rate of 2.5Gbps @ 1.25GHz.