Rainbow Electronics AT89C5132 - Manual (Page 99)

99
AT8xC5132
4173A–8051–08/02
Table 95. MMCON1 Register
MMCON1 (S:E5h) – MMC Control Register 1
Reset Value = 0000 0000b
Table 96. MMCON2 Register
MMCON2 (S:E6h) – MMC Control Register 2
Reset Value = 0000 0000b
7 6 5 4 3 2 1 0
BLEN3 BLEN2 BLEN1 BLEN0 DATDIR DATEN RESPEN CMDEN
Bit
Number
Bit
Mnemonic Description
7 - 4 BLEN3:0
Block Length Bits
Refer to Table 93 for Bits description. Do not program value > 1011b.
3 DATDIR
Data Direction Bit
Set to select data transfer from host to card (write mode).
Clear to select data transfer from card to host (read mode).
2 DATEN
Data Transmission Enable Bit
Set and clear to enable data transmission immediately or after response has
been received.
1 RESPEN
Response Enable Bit
Set and clear to enable the reception of a response following a command
transmission.
0 CMDEN
Command Transmission Enable Bit
Set and clear to enable transmission of the command FIFO to the card.
7 6 5 4 3 2 1 0
MMCEN DCR CCR - - DATD1 DATD0 FLOWC
Bit
Number
Bit
Mnemonic Description
7 MMCEN
MMC Clock Enable Bit
Set to enable the MCLK clocks and activate the MMC controller.
Clear to disable the MMC clocks and freeze the MMC controller.
6 DCR
Data Controller Reset Bit
Set and clear to reset the data line controller in case of transfer abort.
5 CCR
Command Controller Reset Bit
Set and clear to reset the command line controller in case of transfer abort.
4 - 3 -
Reserved
The values read from these Bits are always 0. Do not set these Bits.
2 - 1 DATD1:0
Data Transmission Delay Bits
Used to delay the data transmission after a response from 2 MMC clock periods
(all Bits cleared) to 8 MMC clock periods (all Bits set) by step of 2 MMC clock
periods.
0 FLOWC
MMC Flow Control Bit
Set to enable the flow control during data transfers.
Clear to disable the flow control during data transfers.