Rainbow Electronics AT89C5132 - Manual (Page 14)

14
AT8xC5132
4173A–8051–08/02
Figure 9. PLL Filter Connection
PLL Programming The PLL is programmed using the flow shown in Figure 10. As soon as clock generation
is enabled, the user must wait until the lock indicator is set to ensure the clock output is
stable. The PLL clock frequency will depend on the audio interface clock frequencies.
Figure 10. PLL Programming Flow
V
SS
PFILT
R
C1
C2
V
SS
PLL
Programming
Configure Dividers
N6:0 = xxxxxxb
R9:0 = xxxxxxxxxxb
Enable PLL
PLLRES = 0
PLLEN = 1
PLL Locked?
PLOCK = 1?