Rainbow Electronics AT89C5132 - Manual (Page 36)

36
AT8xC5132
4173A–8051–08/02
Interrupt System
The AT8xC5132, like other control-oriented computer architectures, employ a program
interrupt method. This operation branches to a subroutine and performs some service in
response to the interrupt. When the subroutine terminates, execution resumes at the
point where the interrupt occurred. Interrupts may occur as a result of internal
AT8xC5132 activity (e.g., timer overflow) or at the initiation of electrical signals external
to the microcontroller (e.g., keyboard). In all cases, interrupt operation is programmed
by the system designer, who determines priority of interrupt service relative to normal
code execution and other interrupt service routines. All of the interrupt sources are
enabled or disabled by the system designer and may be manipulated dynamically.
A typical interrupt event chain occurs as follows:
1. An internal or external device initiates an interrupt-request signal. The
AT8xC5132, latch this event into a flag buffer.
2. The priority of the flag is compared to the priority of other interrupts by the inter-
rupt handler. A high priority causes the handler to set an interrupt flag.
3. This signals the instruction execution unit to execute a context switch. This con-
text switch breaks the current flow of instruction sequences. The execution unit
completes the current instruction prior to a save of the program counter (PC) and
reloads the PC with the start address of a software service routine.
4. The software service routine executes assigned tasks and as a final activity per-
forms a RETI (return from interrupt) instruction. This instruction signals
completion of the interrupt, resets the interrupt-in-progress priority and reloads
the program counter. Program operation then continues from the original point of
interruption.
Table 47. Interrupt System Signals
Six interrupt registers are used to control the interrupt system. Two 8-bit registers are
used to enable separately the interrupt sources: IEN0 and IEN1 registers (see Table 50
and Table 51).
Four 8-bit registers are used to establish the priority level of the thirteen sources: IPH0,
IPL0, IPH1 and IPL1 registers (see Table 52 to Table 55).
Interrupt System
Priorities Each of the eleven interrupt sources on the AT8xC5132 can be individually programmed
to one of four priority levels. This is accomplished by one bit in the Interrupt Priority High
registers (IPH0 and IPH1) and one bit in the Interrupt Priority Low registers (IPL0 and
IPL1). This provides each interrupt source four possible priority levels according to
Table 48.
Signal
Name Type Description
Alternate
Function
INT0 I
External Interrupt 0
See Section "External Interrupts", page 39.
P3.2
INT1 I
External Interrupt 1
See Section “External Interrupts”, page 39.
P3.3
KIN3:0 I
Keyboard Interrupt Inputs
See Section “Keyboard Interface”, page 134.
P1.3:0