Rainbow Electronics AT89C5132 - Manual (Page 76)

76
AT8xC5132
4173A–8051–08/02
Table 77. UEPCONX Register
UEPCONX (S:D4h) – USB Endpoint X Control Register (X = EPNUM set in UEPNUM)
Reset Value = 0000 0000b
7 6 5 4 3 2 1 0
EPEN - - - DTGL EPDIR EPTYPE1 EPTYPE0
Bit
Number
Bit
Mnemonic Description
7 EPEN
Endpoint Enable Bit
Set to enable the endpoint according to the device configuration. Endpoint 0 shall
always be enabled after a hardware or USB bus reset and participate in the
device configuration.
Clear to disable the endpoint according to the device configuration.
6 - 4 -
Reserved
The values read from this bit is always 0. Do not set this bit.
3 DTGL
Data Toggle Status Bit (Read-only)
Set by hardware when a DATA1 packet is received.
Cleared by hardware when a DATA0 packet is received.
Note: When a new data packet is received without DTGL toggling from 1 to 0 or 0
to 1, a packet may have been lost. When this occurs for a Bulk endpoint, the
device firmware shall consider the host has retried transmitting a properly
received packet because the host has not received a valid ACK, then the
firmware shall discard the new packet (N.B. The endpoint resets to DATA0 only
upon configuration).
For interrupt endpoints, data toggling is managed as for Bulk endpoints when
used.
For Control endpoints, each SETUP transaction starts with a DATA0 and data
toggling is then used as for Bulk endpoints until the end of the Data stage (for a
control write transfer); the Status stage completes the data transfer with a DATA1
(for a control read transfer).
For Isochronous endpoints, the device firmware shall retrieve every new data
packet and may ignore this bit.
2 EPDIR
Endpoint Direction Bit
Set to configure IN direction for Bulk, Interrupt and Isochronous endpoints.
Clear to configure OUT direction for Bulk, Interrupt and Isochronous endpoints.
This bit has no effect for Control endpoints.
1 - 0
EPTYPE1:
0
Endpoint Type Bits
Set this field according to the endpoint configuration (Endpoint 0 shall always be
configured as Control):
0
0 Control endpoint
0 1 Isochronous endpoint
1 0 Bulk endpoint
1 1 Interrupt endpoint