Rainbow Electronics AT89C5132 - Manual (Page 131)

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AT8xC5132
4173A–8051–08/02
Figure 108. ADC Configuration Flow
Conversion Launching The conversion is launched by setting the ADSST bit in ADCON register, this bit
remains set during the conversion. As soon as the conversion is started, it takes 11
clock periods (T
CONV
) before the data is available in ADDH and ADDL registers.
Figure 109. ADC Conversion Launching Flow
End of Conversion The end of conversion is signalled by the ADEOC flag in ADCON register becoming set
or by the ADSST bit in ADCON register becoming cleared.
The ADEOC flag can generate an interrupt if enabled by setting EADC bit in IEN1 regis-
ter. This flag is set by hardware and must be reset by software.
ADC
Configuration
Enable ADC
ADIDL = x
ADEN = 1
Wait Setup Time
Program ADC Clock
ADCD4:0 = xxxxxb
ADC
Conversion Start
Select Channel
ADCS = 0-1
Start Conversion
ADSST = 1