Rainbow Electronics AT89C5132 - Manual (Page 48)

48
AT8xC5132
4173A–8051–08/02
Exiting Power-down Mode If V
DD
was reduced during the Power-down mode, do not exit Power-down mode until
V
DD
is restored to the normal operating level.
There are two ways to exit the Power-down mode:
1. Generate an enabled external interrupt.
• The AT8xC5132 provides capability to exit from Power-down using INT0, INT1, and
KIN3:0 inputs. In addition, using KIN input provides high or low level exit capability
(see Section “Keyboard Interface”, page 134).
Hardware clears PD bit in PCON register which starts the oscillator and restores the
clocks to the CPU and peripherals. Using INTx input, execution resumes when the
input is released (see Figure 25) while using KINx input, execution resumes after
counting 1024 clock ensuring the oscillator is restarted properly (see Figure 26).
This behavior is necessary for decoding the key while it is still pressed. In both
cases, execution resumes with the interrupt service routine. Upon completion of the
interrupt service routine, program execution resumes with the instruction
immediately following the instruction that activated Power-down mode.
Note: 1. The external interrupt used to exit Power-down mode must be configured as level
sensitive (INT0 and INT1) and must be assigned the highest priority. In addition, the
duration of the interrupt must be long enough to allow the oscillator to stabilize. The
execution will only resume when the interrupt is deasserted.
2. Exit from power-down by external interrupt does not affect the SFRs nor the internal
RAM content.
Figure 25. Power-down Exit Waveform Using INT1:0
Figure 26. Power-down Exit Waveform Using KIN3:0
Note: 1. KIN3:0 can be high or low level triggered.
2. Generate a reset.
– A logic high on the RST pin clears the PD bit in PCON register directly and
asynchronously. This starts the oscillator and restores the clock to the CPU
and peripherals. Program execution momentarily resumes with the
instruction immediately following the instruction that activated Power-down
mode and may continue for a number of clock cycles before the internal
INT1:0
OSC
Power-down phase Oscillator restart phase Active phase Active phase
KIN3:0 1
OSC
Power-down phase 1024 clock count Active phase Active phase