Rainbow Electronics AT89C5132 - Manual (Page 127)

127
AT8xC5132
4173A–8051–08/02
Slave Mode with Interrupt
Policy Figure 102 shows the initialization phase and the transfer phase flows using the inter-
rupt policy.
The transfer format depends on the master controller.
Reading SPSTA at the beginning of the ISR is mandatory for clearing the SPIF flag.
Clear is effective when reading SPDAT.
Figure 104. Slave SPI Interrupt Policy Flows
Registers Table 114. SPCON Register
SPCON (S:C3h) – SPI Control Register
SPI Initialization
Interrupt Policy
Enable Interrupt
ESPI =1
SPI Interrupt
Service Routine
Select Slave Mode
MSTR = 0
Select Format
Program CPOL & CPHA
Enable SPI
SPEN = 1
Get Status
Read SPSTA
Prepare New Transfer
Write Data in SPDAT
Get Data Received
Read SPDAT
Prepare Transfer
Write Data in SPDAT
7 6 5 4 3 2 1 0
SPR2 SPEN SSDIS MSTR CPOL CPHA SPR1 SPR0
Bit
Number
Bit
Mnemonic Description
7 SPR2
SPI Rate Bit 2
Refer to Table 113 for bit rate description.
6 SPEN
SPI Enable Bit
Set to enable the SPI interface.
Clear to disable the SPI interface.
5 SSDIS
Slave Select Input Disable Bit
Set to disable SS in both master and slave modes. In slave mode this bit has no
effect if CPHA = 0.
Clear to enable SS in both master and slave modes.
4 MSTR
Master Mode Select
Set to select the master mode.
Clear to select the slave mode.