Rainbow Electronics AT89C5132 - Manual (Page 108)

108
AT8xC5132
4173A–8051–08/02
Internal Baud Rate Generator When using the Internal Baud Rate Generator, the Baud Rate is derived from the over-
flow of the timer. As shown in Figure 77, the Internal Baud Rate Generator is an 8-bit
auto-reload timer feed by the peripheral clock or by the peripheral clock divided by 6
depending on the SPD bit in BDRCON register (see Table 111). The Internal Baud Rate
Generator is enabled by setting BBR bit in BDRCON register. SMOD1 bit in PCON reg-
ister allows doubling of the generated baud rate.
Figure 77. Internal Baud Rate Generator Block Diagram
Synchronous Mode
(Mode 0) Mode 0 is a half-duplex, synchronous mode, which is commonly used to expand the I/0
capabilities of a device with shift registers. The transmit data (TXD) pin outputs a set of
eight clock pulses while the receive data (RXD) pin transmits or receives a byte of data.
The 8-bit data are transmitted and received least-significant bit (LSB) first. Shifts occur
at a fixed Baud Rate (see Section "Baud Rate Selection (Mode 0)", page 109).
Figure 78 shows the serial port block diagram in Mode 0.
Figure 78. Serial I/O Port Block Diagram (Mode 0)
Transmission (Mode 0) To start a transmission mode 0, write to SCON register clearing Bits SM0, SM1.
As shown in Figure 79, writing the byte to transmit to SBUF register starts the transmis-
sion. Hardware shifts the LSB (D0) onto the RXD pin during the first clock cycle
composed of a high level then low level signal on TXD. During the eighth clock cycle the
MSB (D7) is on the RXD pin. Then, hardware drives the RXD pin high and asserts TI to
indicate the end of the transmission.
0
1
Overflow
SPD
BDRCON.1
BRG
(8 Bits)
BRL
(8 Bits)
PER
CLOCK
÷ 6
IBRG
CLOCK
BRR
BDRCON.4
0
1
SMOD1
PCON.7
÷ 2
To Serial Port
BRG
CLOCK
TXD
RXD SBUF Tx SR
SBUF Rx SR
SM1
SCON.6
SM0
SCON.7
Mode Decoder
M3 M2 M1 M0
Mode
Controller
RI
SCON.0
TI
SCON.1
PER
CLOCK
Baud Rate
Controller