Rainbow Electronics AT89C5132 - Manual (Page 128)

128
AT8xC5132
4173A–8051–08/02
Reset Value = 0001 0100b
Note: 1. When the SPI is disabled, SCK outputs high level.
Table 115. SPSTA Register
SPSTA (S:C4h) – SPI Status Register
Reset Value = 00000 0000b
Table 116. SPDAT Register
SPDAT (S:C5h) – Synchronous Serial Data Register
Reset Value = XXXX XXXXb
3 CPOL
SPI Clock Polarity Bit (1)
Set to have the clock output set to high level in idle state.
Clear to have the clock output set to low level in idle state.
2 CPHA
SPI Clock Phase Bit
Set to have the data sampled when the clock returns to idle state (see CPOL).
Clear to have the data sampled when the clock leaves the idle state (see CPOL).
1 - 0 SPR1:0
SPI Rate Bits 0 and 1
Refer to Table 113 for bit rate description.
7 6 5 4 3 2 1 0
SPIF WCOL - MODF - - - -
Bit
Number
Bit
Mnemonic Description
7 SPIF
SPI Interrupt Flag
Set by hardware when an 8-bit shift is completed.
Cleared by hardware when reading or writing SPDAT after reading SPSTA.
6 WCOL
Write Collision Flag
Set by hardware to indicate that a collision has been detected.
Cleared by hardware to indicate that no collision has been detected.
5 -
Reserved
The values read from this bit is indeterminate. Do not set this bit.
4 MODF
Mode Fault
Set by hardware to indicate that the SS pin is at an appropriate level.
Cleared by hardware to indicate that the SS pin is at an inappropriate level.
3:0 -
Reserved
The values read from these Bits are indeterminate. Do not set these Bits.
7 6 5 4 3 2 1 0
SPD7 SPD6 SPD5 SPD4 SPD3 SPD2 SPD1 SPD0
Bit
Number
Bit
Mnemonic Description
7 - 0 SPD7:0 Synchronous Serial Data
Bit
Number
Bit
Mnemonic Description