Rainbow Electronics AT89C5132 User Manual

Page 74

AT8xC5132

4173A–8051–08/02

Table 73. USBADDR Register

USBADDR (S:C6h) – USB Address Register

Reset Value = 0000 0000b

Table 74. USBINT Register

USBINT (S:BDh) – USB Global Interrupt Register

Reset Value = 0000 0000b

FEN

UADD6

UADD5

UADD4

UADD3

UADD2

UADD1

UADD0

Bit

Number

Bit

Mnemonic

Description

FEN

Function Enable Bit
Set to enable the function. The device firmware shall set this bit after it has
received a USB reset and participate in the following configuration process with
the default address (FEN is reset to 0).
Cleared by hardware at power-up, should not be cleared by the device firmware
once set.

6-0

UADD6:0

USB Address Bits
This field contains the default address (0) after power-up or USB bus reset.
It shall be written with the value set by a SET_ADDRESS request received by
the device firmware.

WUPCPU

EORINT

SOFINT

SPINT

Bit

Number

Bit

Mnemonic Description

7 - 6

Reserved
The values read from these Bits are always 0. Do not set these Bits.

WUPCPU

Wake Up CPU Interrupt Flag
Set by hardware when the USB controller is in SUSPEND state and is re-activated
by a non-idle signal from USB line (not by an upstream resume). This triggers a USB
interrupt when EWUPCPU is set in the USBIEN.
Cleared by software after re-enabling all USB clocks.

EORINT

End of Reset Interrupt Flag
Set by hardware when a End of Reset has been detected by the USB controller. This
triggers a USB interrupt when EEORINT is set in USBIEN.
Cleared by software.

SOFINT

Start of Frame Interrupt Flag
Set by hardware when a USB Start of Frame packet (SOF) has been properly
received. This triggers a USB interrupt when ESOFINT is set in USBIEN.
Cleared by software.

2 - 1

Reserved
The values read from these Bits are always 0. Do not set these Bits.

SPINT

Suspend Interrupt Flag
Set by hardware when a USB Suspend (Idle bus for three frame periods: a J state for
3 ms) is detected. This triggers a USB interrupt when ESPINT is set in USBIEN.
Cleared by software.