Audio buffer, Figure 43, th – Rainbow Electronics AT89C5132 User Manual
Page 63
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AT8xC5132
4173A–8051–08/02
Figure 43. Audio Output Format
The data converter receives its audio stream from two sources selected by the SRC bit
in AUDCON1 register.
As soon as first audio data is input to the data converter, it enables the clock generator
for generating the bit and word clocks.
Audio Buffer
In voice or sound playing mode, the audio stream comes from the C51 core through an
audio buffer. The data is in 8-bit format and is sampled at 8 kHz. The audio buffer
adapts the sample format and rate. The sample format is extended to 16 Bits by filling
the LSB to 00h. Rate is adapted to the DAC rate by duplicating the data using DUP1:0
Bits in AUDCON1 register according to Table 66.
The audio buffer interfaces to the C51 core through three flags: the sample request flag
(SREQ in AUDSTA register), the under-run flag (UNDR in AUDSTA register) and the
busy flag (AUBUSY in AUDSTA register). SREQ and UNDR can generate an interrupt
request as explained in Section "Interrupt Request", page 64. The buffer size is 8 Bytes
large. SREQ is set when the samples number switches from 4 to 3 and reset when the
samples number switches from 4 to 5; UNDR is set when the buffer becomes empty sig-
naling that the audio interface ran out of samples; and AUBUSY is set when the buffer is
full.
DSEL
DCLK
DOUT
MSB
I2S Format with DSIZ = 0 and JUST4:0 = 00001.
LSB
B14
MSB
LSB
B14
B1
B1
DSEL
DCLK
DOUT
MSB
I2S Format with DSIZ = 1 and JUST4:0 = 00001.
LSB
B14
MSB
LSB
B14
1
2
3
13
14
15
16
1
2
3
13
14
15
16
Left Channel
Right Channel
1
2
3
17
18
32
1
2
3
17
18
32
DSEL
DCLK
DOUT
B14
MSB/LSB Justified Format with DSIZ = 0 and JUST4:0 = 00000.
MSB
B1
B15
MSB
B1
LSB
LSB
1
2
3
13
14
15
16
1
2
3
13
14
15
16
Left Channel
Right Channel
Left Channel
Right Channel
DSEL
DCLK
DOUT
16-bit LSB Justified Format with DSIZ = 1 and JUST4:0 = 10000.
1
16
18
32
32
Left Channel
Right Channel
17
31
MSB B14
LSB
B1
MSB B14
LSB
B1
1
16
18
17
31
DSEL
DCLK
DOUT
18-bit LSB Justified Format with DSIZ = 1 and JUST4:0 = 01110.
1
15
30
32
Left Channel
Right Channel
16
31
MSB B16
B2
1
B1
LSB
MSB B16
B2
B1
LSB
15
30
32
16
31