Rainbow Electronics ATmega161L - Manual (Page 86)

86
ATmega161(L)
1228C–AVR–08/02
Figure 49. External Memory with Page Select
Figure 50. External Data Memory Cycles without Wait State (SRWn1 = 0 and SRWn0
=0)
(1)
Note: 1. SRWn1 = SRW11 (upper page) or SRW01 (lower page), SRWn0 = SRW10 (upper
page) or SRW00 (lower page).
The ALE pulse in period T4 is only present if the next instruction accesses the RAM
(internal or external). The Data and Address will only change in T4 if ALE is present
(the next instruction accesses the RAM).
$0000
Data Memory
$0460
External Memory
(0-63K x 8)
$FFFF
Internal memory
SRL[2..0]
SRW11
SRW10
SRW01
SRW00
Lower page
Upper page
System Clock Ø
ALE
WR
RD
Data/Address [7..0]
Data/Address [7..0]
Address [15..8]
Address
Address
Address
T1 T2 T3
XX
Data
Data
Wr
ite
Read
T4
XX
XX
XX
XX
Prev. addr.
XX Prev. data
XX Prev. data