Rainbow Electronics ATmega161L - Manual (Page 137)

137
ATmega161(L)
1228C–AVR–08/02
Figure 85. External Memory Timing (SRWn1 = 1, SRWn0 = 0)
Figure 86. External Memory Timing (SRWn1 = 1, SRWn0 = 1) (1)
Note: 1. The ALE pulse in the last period (T4 - T7) is only present if the next instruction
accesses the RAM (internal or external). The data and address will only change in T4
- T7 if ALE is present (the next instruction accesses the RAM).
ALE
WR
RD
Address [15..8] Address XX XX
Read
Data/Address [7..0] Address Data XX
Wr
ite
Data/Address [7..0] Address Data XX
T1 T2 T3 T6
1
4
2
7
6
3a
3b
5
8 12
16
13
15
9
10
11
14
Prev. addr.
XX Prev. data
XX Prev. data
System Clock Ø
T4 T5
ALE
WR
RD
Address [15..8] Address XX XX
Read
Data/Address [7..0] Address Data XX
Wr
ite
Data/Address [7..0] Address Data XX
T1 T2 T3 T7
1
4
2
7
6
3a
3b
5
8 12
16
13
15
9
10
11
14
Prev. addr.
XX Prev. data
XX Prev. data
T4 T5 T6
System Clock Ш