Rainbow Electronics ATmega161L - Manual (Page 17)

17
ATmega161(L)
1228C–AVR–08/02
Program execution continues at address contained by the Z-register (i.e., the PC is
loaded with the contents of the Z-register).
Relative Program Addressing,
RJMP and RCALL Figure 19. Relative Program Memory Addressing
Program execution continues at address PC + k + 1. The relative address k is -2048 to
2047.
Direct Program Addressing,
JMP and CALL Figure 20. Direct Program Addressing
Program execution continues at the address immediate in the instruction words.
Memory Access Times
and Instruction
Execution Timing This section describes the general access timing concepts for instruction execution and
internal memory access.
The AVR CPU is driven by the System Clock Ø, directly generated from the external
clock crystal for the chip. No internal clock division is used.
Figure 21 shows the parallel instruction fetches and instruction executions enabled by
the Harvard architecture and the fast-access Register File concept. This is the basic
pipelining concept to obtain up to 1 MIPS per MHz with the corresponding unique results
for functions per cost, functions per clocks and functions per power unit.
$1FFF
$000
PROGRAM MEMORY
15
PC
15 12 11
OP k
0
0
OP
16 21 20 31
15 0
16 LSBs
PROGRAM MEMORY
$0000
$1FFF