Rainbow Electronics ATmega161L - Manual (Page 67)

67
ATmega161(L)
1228C–AVR–08/02
• Bits 1, 0 – SPR1, SPR0: SPI Clock Rate Select 1 and 0
These two bits control the SCK rate of the device configured as a Master. SPR1 and
SPR0 have no effect on the Slave. The relationship between SCK and the Oscillator
Clock frequency (f
cl
) is shown in Table 23:
Note: 1. When the SPI is configured as Slave, the SPI is only guaranteed to work at f
cl
/4.
SPI Status Register – SPSR
• Bit 7 – SPIF: SPI Interrupt Flag
When a serial transfer is complete, the SPIF bit is set (one) and an interrupt is gener-
ated if SPIE in SPCR is set (one) and global interrupts are enabled. If SS is an input and
is driven low when the SPI is in Master mode, this will also set the SPIF Flag. SPIF is
cleared by hardware when executing the corresponding Interrupt Handling Vector. Alter-
natively, the SPIF bit is cleared by first reading the SPI Status Register with SPIF set
(one), then by accessing the SPI Data Register (SPDR).
• Bit 6 – WCOL: Write Collision Flag
The WCOL bit is set if the SPI Data Register (SPDR) is written during a data transfer.
The WCOL bit (and the SPIF bit) are cleared (zero) by first reading the SPI Status Reg-
ister with WCOL set (one), and then by accessing the SPI Data Register.
• Bits 5..1 – Res: Reserved Bits
These bits are reserved bits in the ATmega161 and will always read as zero.
• Bit 0
–
SPI2X: Double SPI Speed Bit
When this bit is set (one), the SPI speed (SCK frequency) will be doubled when the SPI
is in Master mode (see Table 23). This means that the maximum SCK period will be two
CPU clock periods. When the SPI is configured as Slave, the SPI is only guaranteed to
work at f
cl
/4.
The SPI interface on the ATmega161 is also used for Program memory and EEPROM
downloading or uploading. See page 125 for serial programming and verification.
Table 23. Relationship between SCK and the Oscillator Frequency (1)
SPI2X SPR1 SPR0 SCK Frequency
0 0 0 f
cl
/4
0 0 1 f
cl
/16
0 1 0 f
cl
/64
0 1 1 f
cl
/128
1 0 0 f
cl
/2
1 0 1 f
cl
/8
1 1 0 f
cl
/32
1 1 1 f
cl
/64
Bit 7 6 5 4 3 2 1 0
$0E ($2E) SPIF WCOL – – – – – SPI2X SPSR
Read/Write R R R R R R R R/W
Initial Value 0 0 0 0 0 0 0 0