Rainbow Electronics ATmega161L - Manual (Page 34)

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ATmega161(L)
1228C–AVR–08/02
Compare match InterruptA Enable) and the OCF2 are set (one), the Timer/Counter2
Compare match Interrupt is executed.
• Bit 1 – TOV0: Timer/Counter0 Overflow Flag
The bit TOV0 is set (one) when an overflow occurs in Timer/Counter0. TOV0 is cleared
by hardware when executing the corresponding Interrupt Handling Vector. Alternatively,
TOV0 is cleared by writing a logical “1” to the Flag. When the SREG I-bit and TOIE0
( T i m e r / C o u n te r0 O v e r f l o w In t e rr u p t En a b l e ) a n d T O V 0 a re s e t ( o n e ) , t h e
Timer/Counter0 Overflow interrupt is executed.
• Bit 2 – OCF0: Output Compare Flag 0
The OCF0 bit is set (one) when compare match occurs between the Timer/Counter0
and the data in OCR0 (Output Compare Register 0). OCF0 is cleared by hardware when
executing the corresponding Interrupt Handling Vector. Alternatively, OCF0 is cleared
by writing a logical “1” to the Flag. When the I-bit in SREG and OCIE0 (Timer/Counter0
Compare match InterruptA Enable) and the OCF0 are set (one), the Timer/Counter0
Compare match Interrupt is executed.
External Interrupts The external interrupts are triggered by the INT0, INT1, and INT2 pins. Observe that, if
enabled, the interrupts will trigger even if the INT0/INT1/INT2 pins are configured as out-
puts. This feature provides a way of generating a software interrupt. The external
interrupts can be triggered by a falling or rising edge or a low level (INT2 is only an edge
triggered interrupt). This is set up as indicated in the specification for the MCU Control
Register – MCUCR (INT0/INT1) and EMCUCR (INT2). When the external interrupt is
enabled and is configured as level triggered (only INT0/INT1), the interrupt will trigger as
long as the pin is held low.
MCU Control Register –
MCUCR The MCU Control Register contains control bits for general MCU functions.
• Bit 7
–
SRE: External SRAM Enable
When the SRE bit is set (one), the external Data memory interface is enabled and the
pin functions AD0 - 7 (Port A), A8 - 5 (Port C), ALE (Port E), WR, and RD (Port D) are
activated as the alternate pin functions. The SRE bit overrides any pin direction settings
in the respective Data Direction Registers. See Figure 50 through Figure 53 for a
description of the external memory pin functions. When the SRE bit is cleared (zero),
the external Data memory interface is disabled and the normal pin and data direction
settings are used.
• Bit 6 – SRW10: External SRAM Wait State
The SRW10 bit is used to set up extra wait states in the external memory interface. See
“Double-speed Transmission” on page 78 for a detailed description.
• Bit 5
–
SE: Sleep Enable
The SE bit must be set (one) to make the MCU enter the Sleep mode when the SLEEP
instruction is executed. To avoid the MCU entering the Sleep mode unless it is the pro-
Bit 7 6 5 4 3 2 1 0
$35 ($55) SRE SRW10 SE SM1 ISC11 ISC10 ISC01 ISC00 MCUCR
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value 0 0 0 0 0 0 0 0