Rainbow Electronics ATmega161L - Manual (Page 75)

75
ATmega161(L)
1228C–AVR–08/02
• Bit 2 – Res: Reserved Bit
This bit is reserved bit in the ATmega161 and will always read as zero.
• Bit 1
–
U2X0/U2X1: Double the UART Transmission Speed
When this bit is set (one), the UART speed will be doubled. This means that a bit will be
transmitted/received in 8 CPU clock periods instead of 16 CPU clock periods. For a
detailed description, see “Double-speed Transmission” on page 78.
• Bit 0 – MPCM0/MPCM1: Multi-processor Communication Mode
This bit is used to enter Multi-processor Communication mode. The bit is set when the
Slave MCU waits for an address byte to be received. When the MCU has been
addressed, the MCU switches off the MPCMn bit and starts data reception.
For a detailed description, see “Multi-processor Communication mode”.
UART0 Control and Status
Registers – UCSR0B
UART1 Control and Status
Registers – UCSR1B
• Bit 7
–
RXCIE0/RXCIE1: RX Complete Interrupt Enable
When this bit is set (one), a setting of the RXCn bit in UCSRnA will cause the Receive
Complete interrupt routine to be executed, provided that global interrupts are enabled.
• Bit 6 – TXCIE0/TXCIE1: TX Complete Interrupt Enable
When this bit is set (one), a setting of the TXCn bit in UCSRnA will cause the Transmit
Complete interrupt routine to be executed, provided that global interrupts are enabled.
• Bit 5 – UDRIE0/UDREI1: UART Data Register Empty Interrupt Enable
When this bit is set (one), a setting of the UDREn bit in UCSRnA will cause the UART
Data Register Empty interrupt routine to be executed, provided that global interrupts are
enabled.
• Bit 4 – RXEN0/RXEN1: Receiver Enable
This bit enables the UART Receiver when set (one). When the Receiver is disabled, the
TXCn, ORn and FEn Status Flags cannot become set. If these flags are set, turning off
RXEN does not cause them to be cleared.
• Bit 3
–
TXEN0/TXEN1: Transmitter Enable
This bit enables the UART Transmitter when set (one). When disabling the Transmitter
while transmitting a character, the Transmitter is not disabled before the character in the
Shift Register plus any following character in UDRn has been completely transmitted.
Bit 7 6 5 4 3 2 1 0
$0A ($2A) RXCIE0 TXCIE0 UDRIE0 RXEN0 TXEN0 CHR90 RXB80 TXB80 UCSR0B
Read/Write R/W R/W R/W R/W R/W R/W R R/W
Initial Value 0 0 0 0 0 0 1 0
Bit 7 6 5 4 3 2 1 0
$01 ($21) RXCIE1 TXCIE1 UDRIE1 RXEN1 TXEN1 CHR91 RXB81 TXB81 UCSR1B
Read/Write R/W R/W R/W R/W R/W R/W R R/W
Initial Value 0 0 0 0 0 0 1 0