Rainbow Electronics ATmega161L - Manual (Page 102)

102
ATmega161(L)
1228C–AVR–08/02
Port D Schematics Note that all port pins are synchronized. The synchronization latches are, however, not
shown in the figures.
Figure 64. Port D Schematic Diagram (Pin PD0)
Figure 65. Port D Schematic Diagram (Pin PD1)
DA
T
A
BUS
D
D
Q
Q
RESET
RESET
C
C
WD
WP
RD
MOS
PULL-
UP
PD0
RXD0
RXEN0 WP:
WD:
RL:
RP:
RD:
RXD0:
RXEN0: WRITE PORTD
WRITE DDRD
READ PORTD LATCH
READ PORTD PIN
READ DDRD
UART0 RECEIVE DATA
UART0 RECEIVE ENABLE
DDD0
PORTD0
RL
RP
DA
T
A
BUS
D
D
Q
Q
RESET
RESET
C
C
WD
WP
RD
RP
RL
MOS
PULL-
UP
PD1
R
R
WP:
WD:
RL:
RP:
RD:
TXD0:
TXEN0: WRITE PORTD
WRITE DDRD
READ PORTD LATCH
READ PORTD PIN
READ DDRD
UART0 TRANSMIT DATA
UART0 TRANSMIT ENABLE
DDD1
PORTD1
TXEN0
TXD0