Rainbow Electronics ATmega128L - Manual (Page 92)

92
ATmega128(L)
2467B–09/01
mode, refer to Table 54 on page 99, and for phase correct PWM refer to Table 55 on
page 100.
A change of the COM01:0 bits state will have effect at the first compare match after the
bits are written. For non-PWM modes, the action can be forced to have immediate effect
by using the FOC0 strobe bits.
Modes of Operation The mode of operation, i.e. the behavior of the Timer/Counter and the output compare
pins, is defined by the combination of the waveform generation mode (WGM01:0) and
compare output mode (COM01:0) bits. The compare output mode bits do not affect the
counting sequence, while the waveform generation mode bits do. The COM01:0 bits
control whether the PWM output generated should be inverted or not (inverted or non-
inverted PWM). For non-PWM modes the COM01:0 bits control whether the output
should be set, cleared, or toggled at a compare match (
See “Compare Match Output
Unit” on page 91.).
For detailed timing information refer to “Timer/Counter Timing Diagrams” on page 96.
Normal Mode The simplest mode of operation is the normal mode (WGM01:0 = 0). In this mode the
counting direction is always up (incrementing), and no counter clear is performed. The
counter simply overruns when it passes its maximum 8-bit value (TOP = 0xFF) and then
restarts from the bottom (0x00). In normal operation the Timer/Counter overflow flag
(
TOV0 ) will be set in the same timer clock cycle as the TCNT0 becomes zero. The TOV0
flag in this case behaves like a 9th bit, except that it is only set, not cleared. However,
combined with the timer overflow interrupt that automatically clears the
TOV0 flag, the
timer resolution can be increased by software. There are no special cases to consider in
the normal mode, a new counter value can be written anytime.
The output compare unit can be used to generate interrupts at some given time. Using
the output compare to generate waveforms in normal mode is not recommended, since
this will occupy too much of the CPU time.
Clear Timer on Compare
Match (CTC) Mode In clear timer on compare or CTC mode (WGM01:0 = 2), the OCR0 register is used to
manipulate the counter resolution. In CTC mode the counter is cleared to zero when the
counter value (TCNT0) matches the OCR0. The OCR0 defines the top value for the
counter, hence also its resolution. This mode allows greater control of the compare
match output frequency. It also simplifies the operation of counting external events.
The timing diagram for the CTC mode is shown in Figure 37. The counter value
(TCNT0) increases until a compare match occurs between TCNT0 and OCR0, and then
counter (TCNT0) is cleared.