Rainbow Electronics ATmega128L - Manual (Page 168)

168
ATmega128(L)
2467B–09/01
xcki Input from XCK pin (internal Signal). Used for synchronous slave operation.
xcko Clock output to XCK pin (Internal Signal). Used for synchronous master
operation.
fosc XTAL pin frequency (System Clock).
Internal Clock Generation –
The Baud Rate Generator Internal clock generation is used for the asynchronous and the synchronous master
modes of operation. The description in this section refers to
Figure 79.
The USART Baud Rate Register (UBRR) and the down-counter connected to it function
as a programmable prescaler or baud rate generator. The down-counter, running at sys-
tem clock (fosc), is loaded with the UBRR value each time the counter has counted
down to zero or when the UBRRL register is written. A clock is generated each time the
counter reaches zero. This clock is the baud rate generator clock output (=
fosc/(UBRR+1)). The transmitter divides the baud rate generator clock output by 2, 8 or
16 depending on mode. The baud rate generator output is used directly by the receiver’s
clock and data recovery units. However, the recovery units use a state machine that
uses 2, 8 or 16 states depending on mode set by the state of the UMSEL, U2X and
DDR_XCK bits.
Table 74 contains equations for calculating the baud rate (in bits per second) and for
calculating the UBRR value for each mode of operation using an internally generated
clock source.
Note: 1. The baud rate is defined to be the transfer rate in bit per second (bps).
BAUD Baud rate (in bits per second, bps)
f
OSC
System oscillator clock frequency
UBRR Contents of the UBRRH and UBRRL registers, (0 - 4095)
Some examples of UBRR values for some system clock frequencies are found in Table
82 (see page 187).
Double Speed Operation
(U2X) The transfer rate can be doubled by setting the U2X bit in UCSRA. Setting this bit only
has effect for the asynchronous operation. Set this bit to zero when using synchronous
operation.
Setting this bit will reduce the divisor of the baud rate divider from 16 to 8, effectively
doubling the transfer rate for asynchronous communication. Note however that the
receiver will in this case only use half the number of samples (reduced from 16 to 8) for
data sampling and clock recovery, and therefore a more accurate baud rate setting and
system clock are required when this mode is used. For the transmitter, there are no
downsides.
Table 74. Equations for Calculating Baud Rate Register Setting
Operating Mode
Equation for Calculating
Baud Rate (1)
Equation for Calculating
UBRR Value
Asynchronous Normal Mode
(U2X = 0)
Asynchronous Double Speed
Mode (U2X = 1)
Synchronous Master Mode
BAUD
f
OSC
16 UBRR 1 +
( )
--------------------------------------- = UBRR
f
OS C
16BAUD
------------------------ 1 – =
BAUD
f
O SC
8 UBRR 1 +
( )
----------------------------------- = UBRR
f
OSC
8BAUD
-------------------- 1 – =
BAUD
f
O SC
2 UBRR 1
+
( )
----------------------------------- = UBRR
f
OSC
2BAUD
-------------------- 1 – =