Input capture register 1 – icr1h and icr1l, Input capture register 3 – icr3h and icr3l, Timer/counter interrupt mask register – timsk – Rainbow Electronics ATmega128L User Manual
Page 134: Atmega128(l)
134
ATmega128(L)
2467B–09/01
Input Capture Register 1 –
ICR1H and ICR1L
Input Capture Register 3 –
ICR3H and ICR3L
The input capture is updated with the counter (TCNTn) value each time an event occurs
on the ICPn pin (or optionally on the analog comparator output for Timer/Counter1). The
input capture can be used for defining the counter TOP value.
The input capture register is 16 bit in size. To ensure that both the high and low bytes
are read simultaneously when the CPU accesses these registers, the access is per-
formed using an 8-bit temporary high byte register (TEMP). This temporary register is
shared by all the other 16-bit registers.
See “Accessing 16-bit Registers” on page 109.
Timer/Counter Interrupt Mask
Register – TIMSK
Note:
This register contains interrupt control bits for several timer/counters, but only timer 1 bits
are described in this section. The remaining bits are described in their respective timer
sections.
• Bit 5 - TICIE1: Timer/Counter 1, Input Capture Interrupt Enable
When this bit is written to one, and the I-flag in the status register is set (interrupts glo-
bally enabled), the timer/counter 1 input capture interrupt is enabled. The corresponding
interrupt vector (
See “Interrupts” on page 54.) is executed when the ICF1 flag, located in
TIFR, is set.
• Bit 4 - OCIE1A: Timer/Counter 1, Output Compare A Match Interrupt Enable
When this bit is written to one, and the I-flag in the status register is set (interrupts glo-
bally enabled), the timer/counter 1 output compare A match interrupt is enabled. The
corresponding interrupt vector (
See “Interrupts” on page 54.) is executed when the
OCF1A flag, located in TIFR, is set.
• Bit 3 - OCIE1B: Timer/Counter 1, Output Compare B Match Interrupt Enable
When this bit is written to one, and the I-flag in the status register is set (interrupts glo-
bally enabled), the timer/counter 1 output compare B match interrupt is enabled. The
corresponding interrupt vector (
See “Interrupts” on page 54.) is executed when the
OCF1B flag, located in TIFR, is set.
• Bit 2 - TOIE1: Timer/Counter 1, Overflow Interrupt Enable
When this bit is written to one, and the I-flag in the status register is set (interrupts glo-
bally enabled), the timer/counter 1 overflow interrupt is enabled. The corresponding
interrupt vector (
See “Interrupts” on page 54.) is executed when the TOV1 flag, located
in TIFR, is set.
Bit
7
6
5
4
3
2
1
0
ICR1[15:8]
ICR1H
ICR1[7:0]
ICR1L
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial value
0
0
0
0
0
0
0
0
Bit
7
6
5
4
3
2
1
0
ICR3[15:8]
ICR3H
ICR3[7:0]
ICR3L
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial value
0
0
0
0
0
0
0
0
Bit
7
6
5
4
3
2
1
0
OCIE2
TOIE2
TICIE1
OCIE1A
OCIE1B
TOIE1
OCIE0
TOIE0
TIMSK
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial value
0
0
0
0
0
0
0
0