Rainbow Electronics ATmega128L - Manual (Page 19)

19
ATmega128(L)
2467B–09/01
Figure 10. On-chip Data SRAM Access Cycles
EEPROM Data Memory The ATmega128 contains 4K bytes of data EEPROM memory. It is organized as a sep-
arate data space, in which single bytes can be read and written. The EEPROM has an
endurance of at least 100,000 write/erase cycles. The access between the EEPROM
and the CPU is described in the following, specifying the EEPROM Address Registers,
the EEPROM Data Register, and the EEPROM Control Register.
For a detailed description of SPI and JTAG data downloading to the EEPROM, see
page 292 and page 297 respectively.
EEPROM Read/Write Access The EEPROM access registers are accessible in the I/O space.
The write access time for the EEPROM is given in Table 2. A self-timing function, how-
ever, lets the user software detect when the next byte can be written. If the user code
contains instructions that write the EEPROM, some precautions must be taken. In
heavily filtered power supplies, V
CC
is likely to rise or fall slowly on power-up/down. This
causes the device for some period of time to run at a voltage lower than specified as
minimum for the clock frequency used.
See “Preventing EEPROM Corruption” on page
23. for details on how to avoid problems in these situations.
In order to prevent unintentional EEPROM writes, a specific write procedure must be fol-
lowed. Refer to the description of the EEPROM Control Register for details on this.
When the EEPROM is read, the CPU is halted for four clock cycles before the next
instruction is executed. When the EEPROM is written, the CPU is halted for two clock
cycles before the next instruction is executed.
EEPROM Address Register –
EEARH and EEARL
• Bits 15..12 - Res: Reserved Bits
These are reserved bits and will always read as zero. When writing to this address loca-
tion, write these bits to zero for compatibility with future devices.
clk
WR
RD
Data
Data
Address Address valid
T1 T2 T3
Compute Address
Read
Write
CPU
Memory access instruction Next instruction
Bit 15 14 13 12 11 10 9 8
– – – – EEAR11 EEAR10 EEAR9 EEAR8 EEARH
EEAR7 EEAR6 EEAR5 EEAR4 EEAR3 EEAR2 EEAR1 EEAR0 EEARL
7 6 5 4 3 2 1 0
Read/Write R R R R R/W R/W R/W R/W
R/W R/W R/W R/W R/W R/W R/W R/W
Initial value 0 0 0 0 X X X X
X X X X X X X X