Scanning the analog comparator, Atmega128(l) – Rainbow Electronics ATmega128L User Manual
Page 251
251
ATmega128(L)
2467B–09/01
Figure 127. Boundary-scan Cells for Oscillators and Clock Options
Table 102 summaries the scan registers for the external clock pin XTAL1, oscillators
with XTAL1/XTAL2 connections as well as 32 kHz Timer oscillator.
Notes:
1. Do not enable more than one clock source as main clock at a time.
2. Scanning an oscillator output gives unpredictable results as there is a frequency drift
between the internal oscillator and the JTAG TCK clock. If possible, scanning an
external clock is preferred.
3. The clock configuration is programmed by fuses. As a fuse is not changed run-time,
the clock configuration is considered fixed for a given application. The user is advised
to scan the same clock option as to be used in the final system. The enable signals
are supported in the scan chain because the system logic can disable clock options
in sleep modes, thereby disconnecting the oscillator pins from the scan path if not
provided. The INTCAP fuses are not supported in the scan-chain, so the boundary
scan chain can not make a XTAL oscillator requiring internal capacitors to run unless
the fuse is correctly programmed.
Scanning the Analog
Comparator
The relevant Comparator signals regarding Boundary-scan are shown in
The Boundary-scan cell from
Figure 129 is attached to each of these signals. The sig-
nals are described in
The Comparator need not be used for pure connectivity testing, since all analog inputs
are shared with a digital port pin as well.
Table 102. Scan Signals for the Oscillator
Enable signal
Scanned Clock
Line
Clock Option
Scanned Clock Line
when not Used
EXTCLKEN
EXTCLK (XTAL1)
External Clock
0
OSCON
OSCCK
External Crystal
External Ceramic Resonator
1
RCOSCEN
RCCK
External RC
1
OSC32EN
OSC32CK
Low Freq. External Crystal
1
TOSKON
TOSCK
32 kHz Timer Oscillator
1
0
1
D
Q
From
previous
cell
ClockDR
ShiftDR
To
next
cell
To system logic
FF1
0
1
D
Q
D
Q
G
0
1
From
previous
cell
ClockDR
UpdateDR
ShiftDR
To
next
cell
EXTEST
From digital logic
XTAL1/TOSC1
XTAL2/TOSC2
Oscillator
ENABLE
OUTPUT