Rainbow Electronics ATmega128L - Manual (Page 184)

184
ATmega128(L)
2467B–09/01
• Bit 2 - UPE: Parity Error
This bit is set if the next character in the receive buffer had a Parity Error when received
and the parity checking was enabled at that point (UPM1 = 1). This bit is valid until the
receive buffer (UDR) is read. Always set this bit to zero when writing to UCSRA.
• Bit 1 - U2X: Double the USART Transmission Speed
This bit only has effect for the asynchronous operation. Write this bit to zero when using
synchronous operation.
Writing this bit to one will reduce the divisor of the baud rate divider from 16 to 8 effec-
tively doubling the transfer rate for asynchronous communication.
• Bit 0 - MPCM: Multi-Processor Communication Mode
This bit enables the Multi-processor Communication Mode. When the MPCM bit is writ-
ten to one, all the incoming frames received by the USART receiver that do not contain
address information will be ignored. The transmitter is unaffected by the MPCM setting.
For more detailed information see
“Multi-processor Communication Mode” on page 181.
USART Control and Status
Register B – UCSRB
• Bit 7 - RXCIE: RX Complete Interrupt Enable
Writing this bit to one enables interrupt on the RXC flag. A USART Receive Complete
interrupt will be generated only if the RXCIE bit is written to one, the global interrupt flag
in SREG is written to one and the RXC bit in UCSRA is set.
• Bit 6 - TXCIE: TX Complete Interrupt Enable
Writing this bit to one enables interrupt on the TXC flag. A USART Transmit Complete
interrupt will be generated only if the TXCIE bit is written to one, the global interrupt flag
in SREG is written to one and the TXC bit in UCSRA is set.
• Bit 5 - UDRIE: USART Data Register Empty Interrupt Enable
Writing this bit to one enables interrupt on the UDRE flag. A Data Register Empty inter-
rupt will be generated only if the UDRIE bit is written to one, the global interrupt flag in
SREG is written to one and the UDRE bit in UCSRA is set.
• Bit 4 - RXEN: Receiver Enable
Writing this bit to one enables the USART receiver. The receiver will override normal
port operation for the RxD pin when enabled. Disabling the receiver will flush the receive
buffer invalidating the FE, DOR and UPE flags.
• Bit 3 - TXEN: Transmitter Enable
Writing this bit to one enables the USART transmitter. The transmitter will override nor-
mal port operation for the TxD pin when enabled. The disabling of the transmitter
(writing TXEN to zero) will not become effective until ongoing and pending transmis-
sions are completed, i.e. when the transmit shift register and transmit buffer register do
not contain data to be transmitted. When disabled, the transmitter will no longer override
the TxD port.
• Bit 2 - UCSZ2: Character Size
The UCSZ2 bits combined with the UCSZ1:0 bit in UCSRC sets the number of data bits
(character size) in a frame the receiver and transmitter use.
Bit 7 6 5 4 3 2 1 0
RXCIE TXCIE UDRIE RXEN TXEN UCSZ2 RXB8 TXB8 UCSRB
Read/Write R/W R/W R/W R/W R/W R/W R R/W
Initial value 0 0 0 0 0 0 0 0