Rainbow Electronics ATmega128L - Manual (Page 47)

47
ATmega128(L)
2467B–09/01
Power-on Reset A Power-on Reset (POR) pulse is generated by an on-chip detection circuit. The detec-
tion level is defined in
Table 19. The POR is activated whenever V
CC
is below the
detection level. The POR circuit can be used to trigger the start-up reset, as well as to
detect a failure in supply voltage.
A Power-on Reset (POR) circuit ensures that the device is reset from power-on. Reach-
ing the power-on reset threshold voltage invokes the delay counter, which determines
how long the device is kept in RESET after V
CC
rise. The RESET signal is activated
again, without any delay, when V
CC
decreases below the detection level.
Figure 22. MCU Start-up, RESET Tied to V
CC
.
Figure 23. MCU Start-up, RESET Extended Externally
External Reset An external reset is generated by a low level on the RESET pin. Reset pulses longer
than the minimum pulse width (see
Table 19) will generate a reset, even if the clock is
not running. Shorter pulses are not guaranteed to generate a reset. When the applied
signal reaches the Reset Threshold Voltage – V
RST
on its positive edge, the delay
counter starts the MCU after the Time-out period t
TOUT
has expired.
V
RESET
TIME-OUT
INTERNAL
RESET
t
TOUT
V
POT
V
RST
CC
RESET
TIME-OUT
INTERNAL
RESET
t
TOUT
V
POT
V
RST
V
CC