Rainbow Electronics ATmega128L - Manual (Page 317)

317
ATmega128(L)
2467B–09/01
External Data Memory Timing
Notes: 1. This assumes 50% clock duty cycle. The half period is actually the high time of the external clock, XTAL1.
2. This assumes 50% clock duty cycle. The half period is actually the low time of the external clock, XTAL1.
Table 138. External Data Memory Characteristics, 4.5 - 5.5 Volts, No Wait-state
Symbol Parameter
8 MHz Oscillator Variable Oscillator
Unit Min Max Min Max
0 1/t
CLCL
Oscillator Frequency 0.0 TBD MHz
1 t
LHLL
ALE Pulse Width TBD t
CLCL
-TBD ns
2 t
AVLL
Address Valid A to ALE Low TBD 0.5t
CLCL
-TBD (1) ns
3a t
LLAX_ST
Address Hold After ALE Low,
write access
TBD TBD
ns
3b t
LLAX_LD
Address Hold after ALE Low,
read access
TBD TBD
ns
4 t
AVLLC
Address Valid C to ALE Low TBD 0.5t
CLCL
-TBD (1) ns
5 t
AVRL
Address Valid to RD Low TBD 1.0t
CLCL
-TBD ns
6 t
AVWL
Address Valid to WR Low TBD 1.0t
CLCL
-TBD ns
7 t
LLWL
ALE Low to WR Low TBD TBD 0.5t
CLCL
-TBD (2) 0.5t
CLCL
-TBD (2) ns
8 t
LLRL
ALE Low to RD Low TBD TBD 0.5t
CLCL
-TBD (2) 0.5t
CLCL
-TBD (2) ns
9 t
DVRH
Data Setup to RD High TBD TBD ns
10 t
RLDV
Read Low to Data Valid TBD TBD ns
11 t
RHDX
Data Hold After RD High TBD TBD ns
12 t
RLRH
RD Pulse Width TBD 1.0t
CLCL
-TBD ns
13 t
DVWL
Data Setup to WR Low TBD 0.5t
CLCL
-TBD (1) ns
14 t
WHDX
Data Hold After WR High TBD 0.5t
CLCL
-TBD (1) ns
15 t
DVWH
Data Valid to WR High TBD 1.0t
CLCL
-TBD ns
16 t
WLWH
WR Pulse Width TBD 1.0t
CLCL
-TBD ns
Table 139. External Data Memory Characteristics, 4.5 - 5.5 Volts, 1 Cycle Wait-state
Symbol Parameter
8 MHz Oscillator Variable Oscillator
Unit Min Max Min Max
0 1/t
CLCL
Oscillator Frequency 0.0 TBD MHz
10 t
RLDV
Read Low to Data Valid TBD 2.0t
CLCL
-TBD ns
12 t
RLRH
RD Pulse Width TBD 2.0t
CLCL
-TBD ns
15 t
DVWH
Data Valid to WR High TBD 2.0t
CLCL
-TBD ns
16 t
WLWH
WR Pulse Width TBD 2.0t
CLCL
-TBD ns