Rainbow Electronics ATmega128L - Manual (Page 40)

40
ATmega128(L)
2467B–09/01
• Bit 7 - XDIVEN: XTAL Divide Enable
When the XDIVEN bit is written one, the clock frequency of the CPU and all peripherals
(clk
I/O
, clk
ADC
, clk
CPU
, clk
FLASH
) is divided by the factor defined by the setting of XDIV6 -
XDIV0. This bit can be written run-time to vary the clock frequency as suitable to the
application.
• Bits 6..0 - XDIV6..XDIV0: XTAL Divide Select Bits 6 - 0
These bits define the division factor that applies when the XDIVEN bit is set (one). If the
value of these bits is denoted d, the following formula defines the resulting CPU and
peripherals clock frequency f
CLK
:
The value of these bits can only be changed when XDIVEN is zero. When XDIVEN is
written to one, the value written simultaneously into XDIV6..XDIV0 is taken as the divi-
sion factor. When XDIVEN is written to zero, the value written simultaneously into
XDIV6..XDIV0 is rejected. As the divider divides the master clock input to the MCU, the
speed of all peripherals is reduced when a division factor is used.
f
CLK
Source clock
129 d –
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