Rainbow Electronics ATmega128L - Manual (Page 86)

86
ATmega128(L)
2467B–09/01
External Interrupt Mask
Register – EIMSK
• Bits 7..4 - INT7 - INT0: External Interrupt Request 7 - 0 Enable
When an INT7- INT4 bit is written to one and the I-bit in the Status Register (SREG) is
set (one), the corresponding external pin interrupt is enabled. The Interrupt Sense Con-
trol bits in the External Interrupt Control Registers - EICRA and EICRB defines whether
the external interrupt is activated on rising or falling edge or level sensed. Activity on any
of these pins will trigger an interrupt request even if the pin is enabled as an output. This
provides a way of generating a software interrupt.
External Interrupt Flag
Register - EIFR
• Bits 7..0 - INTF7 - INTF0: External Interrupt Flags 7 - 0
When an edge or logic change on the INT7:0 pin triggers an interrupt request, INTF7:0
becomes set (one). If the I-bit in SREG and the corresponding interrupt enable bit,
INT7:0 in EIMSK, are set (one), the MCU will jump to the interrupt vector. The flag is
cleared when the interrupt routine is executed. Alternatively, the flag can be cleared by
writing a logical one to it. These flags are always cleared when INT7:0 are configured as
level interrupt. Note that when entering sleep mode with the INT3:0 interrupts disabled,
the input buffers on these pins will be disabled. This may cause a logic change in inter-
nal signals which will set the INTF3:0 flags. See
“Digital Input Enable and Sleep Modes”
on page 65 for more information.
Bit 7 6 5 4 3 2 1 0
INT7 INT6 INT5 INT4 INT3 INT2 INT1 IINT0 EIMSK
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial value 0 0 0 0 0 0 0 0
Bit 7 6 5 4 3 2 1 0
INTF7 INTF6 INTF5 INTF4 INTF3 INTF2 INTF1 IINTF0 EIFR
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial value 0 0 0 0 0 0 0 0