Timer/counter interrupt flag register – tifr, Atmega128(l) – Rainbow Electronics ATmega128L User Manual
Page 136
136
ATmega128(L)
2467B–09/01
Timer/Counter Interrupt Flag
Register – TIFR
Note:
This register contains flag bits for several timer/counters, but only timer 1 bits are
described in this section. The remaining bits are described in their respective timer
sections.
• Bit 5 - ICF1: Timer/Counter 1, Input Capture Flag
This flag is set when a capture event occurs on the ICP1 pin. When the Input Capture
Register (ICR1) is set by the WGMn3:0 to be used as the TOP value, the ICF1 flag is set
when the counter reaches the TOP value.
ICF1 is automatically cleared when the Input Capture Interrupt vector is executed. Alter-
natively, ICF1 can be cleared by writing a logic one to its bit location.
• Bit 4 - OCF1A: Timer/Counter 1, Output Compare A Match Flag
This flag is set in the timer clock cycle after the counter (TCNT1) value matches the Out-
put Compare Register A (OCR1A).
Note that a forced output compare (FOC1A) strobe will not set the OCF1A flag.
OCF1A is automatically cleared when the Output Compare Match A interrupt vector is
executed. Alternatively, OCF1A can be cleared by writing a logic one to its bit location.
• Bit 3 - OCF1B: Timer/Counter 1, Output Compare B Match Flag
This flag is set in the timer clock cycle after the counter (TCNT1) value matches the Out-
put Compare Register B (OCR1B).
Note that a forced output compare (FOC1B) strobe will not set the OCF1B flag.
OCF1B is automatically cleared when the Output Compare Match B interrupt vector is
executed. Alternatively, OCF1B can be cleared by writing a logic one to its bit location.
• Bit 2 - TOV1: Timer/Counter 1, Overflow Flag
The setting of this flag is dependent of the WGMn3:0 bits setting. In normal and CTC
modes, the TOV1 flag is set when the timer overflows. Refer to
for the TOV1 flag behavior when using another WGMn3:0 bit setting.
TOV1 is automatically cleared when the Timer/Counter 1 Overflow interrupt vector is
executed. Alternatively, TOV1 can be cleared by writing a logic one to its bit location.
Extended Timer/Counter
Interrupt Flag Register –
ETIFR
• Bit 7:6 - Reserved Bits
These bits are reserved for future use. For ensuring compatibility with future devices,
these bits must be set to zero when ETIFR is written.
• Bit 5 - ICF3: Timer/Counter 3, Input Capture Flag
This flag is set when a capture event occurs on the ICP3 pin. When the Input Capture
Register (ICR3) is set by the WGM3:0 to be used as the TOP value, the ICF3 flag is set
when the counter reaches the TOP value.
Bit
7
6
5
4
3
2
1
0
OCF2
TOV2
ICF1
OCF1A
OCF1B
TOV1
OCF0
TOV0
TIFR
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial value
0
0
0
0
0
0
0
0
Bit
7
6
5
4
3
2
1
0
–
–
ICF3
OCF3A
OCF3B
TOV3
OCF3C
OCF1C
ETIFR
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial value
0
0
0
0
0
0
0
0