Rainbow Electronics ATmega128L - Manual (Page 139)

139
ATmega128(L)
2467B–09/01
Each half period of the external clock applied must be longer than one system clock
cycle to ensure correct sampling. The external clock must be guaranteed to have less
than half the system clock frequency (f
ExtClk
< f
clk_I/O
/2) given a 50/50% duty cycle. Since
the edge detector uses sampling, the maximum frequency of an external clock it can
detect is half the sampling frequency (Nyquist sampling theorem). However, due to vari-
ation of the system clock frequency and duty cycle caused by oscillator source (crystal,
resonator, and capacitors) tolerances, it is recommended that maximum frequency of an
external clock source is less than f
clk_I/O
/2.5.
An external clock source can not be prescaled.
Figure 59. Prescaler for Timer/Counter1, Timer/Counter2, and Timer/Counter3
Note: The synchronization logic on the input pins ( T3/T2/T1) is shown in Figure 58.
Special Function IO Register –
SFIOR
• Bit 7 - TSM: Timer/Counter Synchronization Mode
Writing TSM to one, PSR0 and PSR321 becomes registers that hold their value until
rewritten, or the TSM bit is written zero. This mode is useful for synchronizing
timer/counters. By setting both TSM and the appropriate PSR bit(s), the appropriate
timer/counters are halted, and can be configured to same value without the risk of one of
t h em a d v a n c i ng d u ri ng c o nf i g u ra t i o n . W h e n th e T SM b i t wr i tt e n z e ro , t h e
Timer/Counters start counting simultaneously.
• Bit 0 - PSR321: Prescaler Reset Timer/Counter3, Timer/Counter2, and
Timer/Counter1
Writing PSR321 to one resets the Prescaler for Timer/Counter3, Timer/Counter2, and
Timer/Counter1. The bit will be cleared by hardware after the operation is performed.
Writing a zero to this bit will have no effect. Note that Timer/Counter3 Timer/Counter2,
and Timer/Counter1 share the same prescaler and a reset of this prescaler will affect
both timers. This bit will always be read as zero.
PSR321
Clear
clk T2
TIMER/COUNTER2 CLOCK SOURCE
0
CS20
CS21
CS22
T2
clk T1
TIMER/COUNTER1 CLOCK SOURCE
0
CS10
CS11
CS12
T1
clk T3
TIMER/COUNTER3 CLOCK SOURCE
0
CS30
CS31
CS32
T3
10-BIT T/C PRESCALER CK
CK/8
CK/64 CK/256
CK/1024
Bit 7 6 5 4 3 2 1 0
TSM – – ADHSM ACME PUD PSR0 PSR321 SFIOR
Read/Write R/W R R R/W R/W R/W R/W R/W
Initial value 0 0 0 0 0 0 0 0