Rainbow Electronics ATmega128L - Manual (Page 235)

235
ATmega128(L)
2467B–09/01
ADC Control and Status
Register A – ADCSRA
• Bit 7 - ADEN: ADC Enable
Writing this bit to one enables the ADC. By writing it to zero, the ADC is turned off. Turn-
ing the ADC off while a conversion is in progress, will terminate this conversion.
• Bit 6 - ADSC: ADC Start Conversion
In Single Conversion Mode, write this bit to one to start each conversion. In Free Run-
ning Mode, write this bit to zero to start the first conversion. The first conversion after
ADSC has been written after the ADC has been enabled, or if ADSC is written at the
same time as the ADC is enabled, will take 25 ADC clock cycles instead of the normal
13. This first conversion performs initialization of the ADC.
ADSC will read as one as long as a conversion is in progress. When the conversion is
complete, it returns to zero. Writing zero to this bit has no effect.
• Bit 5 - ADFR: ADC Free Running Select
When this bit is written to one, the ADC operates in Free Running Mode. In this mode,
the ADC samples and updates the data registers continuously. Writing zero to this bit
will terminate Free Running Mode.
• Bit 4 - ADIF: ADC Interrupt Flag
This bit is set when an ADC conversion completes and the data registers are updated.
The ADC Conversion Complete Interrupt is executed if the ADIE bit and the I-bit in
SREG are set. ADIF is cleared by hardware when executing the corresponding interrupt
handling vector. Alternatively, ADIF is cleared by writing a logical one to the flag.
Beware that if doing a read-modify-write on ADCSRA, a pending interrupt can be dis-
abled. This also applies if the SBI and CBI instructions are used.
• Bit 3 - ADIE: ADC Interrupt Enable
When this bit is written to one and the I-bit in SREG is set, the ADC Conversion Com-
plete Interrupt is activated.
• Bits 2:0 - ADPS2:0: ADC Prescaler Select Bits
These bits determine the division factor between the XTAL frequency and the input
clock to the ADC.
11101 ADC5 ADC2 1x
11110 1.22 V (V
BG
) N/A
11111 0 V (GND)
Table 97. Input Channel and Gain Selections (Continued)
MUX4..0
Single Ended
Input Positive Differential
Input Negative Differential
Input
Gain
Bit 7 6 5 4 3 2 1 0
ADEN ADSC ADFR ADIF ADIE ADPS2 ADPS1 ADPS0 ADCSRA
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial value 0 0 0 0 0 0 0 0