Rainbow Electronics ATmega128L - Manual (Page 193)

193
ATmega128(L)
2467B–09/01
Figure 89. Data Packet Format
Combining Address and Data
Packets Into a Transmission A transmission basically consists of a START condition, a SLA+R/W, one or more data
packets and a STOP condition. An empty message, consisting of a START followed by
a STOP condition, is illegal. Note that the Wired-ANDing of the SCL line can be used to
implement handshaking between the master and the slave. The slave can extend the
SCL low period by pulling the SCL line low. This is useful if the clock speed set up by the
master is too fast for the slave, or the slave needs extra time for processing between the
data transmissions. The slave extending the SCL low period will not affect the SCL high
period, which is determined by the master. As a consequence, the slave can reduce the
TWI data transfer speed by prolonging the SCL duty cycle.
Figure 90 shows a typical data transmission. Note that several data bytes can be trans-
mitted between the SLA+R/W and the STOP condition, depending on the software
protocol implemented by the application software.
Figure 90. Typical Data Transmission
Multi-master Bus Systems, Arbitration and Synchronization
The TWI protocol allows bus systems with several masters. Special concerns have
been taken in order to ensure that transmissions will proceed as normal, even if two or
more masters initiate a transmission at the same time. Two problems arise in multi-mas-
ter systems:
• An algorithm must be implemented allowing only one of the masters to complete the
transmission. All other masters should cease transmission when they discover that
they have lost the selection process. This selection process is called arbitration.
When a contending master discovers that it has lost the arbitration process, it
should immediately switch to slave mode to check whether it is being addressed by
the winning master. The fact that multiple masters have started transmission at the
same time should not be detectable to the slaves, i.e. the data being transferred on
the bus must not be corrupted.
1 2 7 8 9
Data MSB Data LSB ACK
Aggregate
SDA
SDA from
transmitter
SDA from
receiver
SCL from
master
SLA+R/W Data byte
STOP, REPEATED
START or next
data byte
1 2 7 8 9
Data Byte
Data MSB Data LSB ACK
SDA
SCL
START
1 2 7 8 9
Addr MSB Addr LSB R/W ACK
SLA+R/W STOP