Rainbow Electronics ATmega128L - Manual (Page 154)

154
ATmega128(L)
2467B–09/01
• Bit 6- TOIE2: Timer/Counter2 Overflow Interrupt Enable
When the TOIE2 bit is written to one, and the I-bit in the Status Register is set (one), the
Timer/Counter2 Overflow interrupt is enabled. The corresponding interrupt is executed if
an overflow in Timer/Counter2 occurs, i.e. when the TOV2 bit is set in the Timer/Counter
Interrupt Flag Register – TIFR.
Timer/Counter Interrupt Flag
Register – TIFR
• Bit 7- OCF2: Output Compare Flag 2
The OCF2 bit is set (one) when a compare match occurs between the Timer/Counter2
and the data in OCR2 - Output Compare Register2. OCF2 is cleared by hardware when
executing the corresponding interrupt handling vector. Alternatively, OCF2 is cleared by
writing a logic one to the flag. When the I-bit in SREG, OCIE2 (Timer/Counter2 Com-
pare match Interrupt Enable), and OCF2 are set (one), the Timer/Counter2 Compare
match Interrupt is executed.
• Bit 6- TOV2: Timer/Counter2 Overflow Flag
The bit TOV2 is set (one) when an overflow occurs in Timer/Counter2. TOV2 is cleared
by hardware when executing the corresponding interrupt handling vector. Alternatively,
TOV2 is cleared by writing a logic one to the flag. When the SREG I-bit, TOIE2
(Ti m e r/ Co u nt e r2 O ver flo w I nt e rru p t E n ab l e ), a n d TOV 2 ar e s e t ( on e ), t h e
Timer/Counter2 Overflow interrupt is executed. In PWM mode, this bit is set when
Timer/Counter2 changes counting direction at $00.
Bit 7 6 5 4 3 2 1 0
OCF2 TOV2 ICF1 OCF1A OCF1B TOV1 OCF0 TOV0 TIFR
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial value 0 0 0 0 0 0 0 0