Atmega128(l) – Rainbow Electronics ATmega128L User Manual
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ATmega128(L)
2467B–09/01
Figure 46. Counter Unit Block Diagram
Signal description (internal signals):
Count
Increment or decrement TCNTn by 1.
Direction
Select between increment and decrement.
Clear
Clear TCNTn (set all bits to zero).
clk
T
n
Timer/counter clock.
TOP
Signalize that TCNTn has reached maximum value.
BOTTOM
Signalize that TCNTn has reached minimum value (zero).
The 16-bit counter is mapped into two 8-bit I/O memory locations: counter high
(TCNTnH) containing the upper 8 bits of the counter, and counter low (TCNTnL) con-
taining the lower 8 bits. The TCNTnH register can only be indirectly accessed by the
CPU. When the CPU does an access to the TCNTnH I/O location, the CPU accesses
the high byte temporary register (TEMP). The temporary register is updated with the
TCNTnH value when the TCNTnL is read, and TCNTnH is updated with the temporary
register value when TCNTnL is written. This allows the CPU to read or write the entire
16-bit counter value within one clock cycle via the 8-bit data bus. It is important to notice
that there are special cases of writing to the TCNTn register when the counter is count-
ing that will give unpredictable results. The special cases are described in the sections
where they are of importance.
Depending on the mode of operation used, the counter is cleared, incremented, or dec-
remented at each timer clock (clk
T
n
). The clk
T
n
can be generated from an external or
internal clock source, selected by the clock select bits (CSn2:0). When no clock source
is selected (CSn2:0 = 0) the timer is stopped. However, the TCNTn value can be
accessed by the CPU, independent of whether clk
T
n
is present or not. A CPU write over-
rides (has priority over) all counter clear or count operations.
The counting sequence is determined by the setting of the waveform generation mode
bits (WGMn3:0) located in the Timer/Counter control registers A and B (TCCRnA and
TCCRnB). There are close connections between how the counter behaves (counts) and
how waveforms are generated on the output compare outputs OCnx. For more details
about advanced counting sequences and waveform generation, see
The Timer/Counter overflow (TOVn) flag is set according to the mode of operation
selected by the WGMn3:0 bits. TOVn can be used for generating a CPU interrupt.
TEMP (8-bit)
DATABUS
(8-bit)
TCNTn (16-bit Counter)
TCNTnH (8-bit) TCNTnL (8-bit)
Control Logic
Count
Clear
Direction
TOVn
(Int.Req.)
Clock Select
TOP
BOTTOM
Tn
Edge
Detector
( From Prescaler )
clk
Tn