Rainbow Electronics ATmega128L - Manual (Page 306)

306
ATmega128(L)
2467B–09/01
Figure 150. Virtual Flash Page Load Register
Virtual Flash Page Read
Register The Virtual Flash Page Read register is a virtual scan chain with length equal to the
number of bits in one Flash page plus 8. Internally the shift register is 8 bit, and the data
are automatically transferred from the Flash data page byte by byte. The first 8 cycles
are used to transfer the first byte to the internal shift register, and the bits that are shifted
out during these 8 cycles should be ignored. Following this initialization, data are shifted
out starting with the LSB of the first instruction in the page and ending with the MSB of
the last instruction in the page. This provides an efficient way to read one full Flash page
to verify programming.
Figure 151. Virtual Flash Page Read Register
Programming Algorithm All references below of type “1a”, “1b”, and so on, refer to Table 132.
TDI
TDO
D
A
T
A
Flash
EEPROM
Fuses
Lock Bits
STROBES
ADDRESS
State
machine
TDI
TDO
D
A
T
A
Flash
EEPROM
Fuses
Lock Bits
STROBES
ADDRESS
State
machine