Rainbow Electronics ATmega128L - Manual (Page 131)

131
ATmega128(L)
2467B–09/01
• Bit 6 - ICESn: Input Capture Edge Select
This bit selects which edge on the Input Capture Pin (ICPn) that is used to trigger a cap-
ture event. When the ICESn bit is written to zero, a falling (negative) edge is used as
trigger, and when the ICESn bit is written to one, a rising (positive) edge will trigger the
capture.
When a capture is triggered according to the ICESn setting, the counter value is copied
into the Input Capture Register (ICRn). The event will also set the Input Capture Flag
(ICFn), and this can be used to cause an Input Capture Interrupt, if this interrupt is
enabled.
When the ICRn is used as TOP value (see description of the WGMn3:0 bits located in
the TCCRnA and the TCCRnB register), the ICPn is disconnected and consequently the
input capture function is disabled.
• Bit 5 - Reserved Bit
This bit is reserved for future use. For ensuring compatibility with future devices, this bit
must be written to zero when TCCRnB is written.
• Bit 4:3 - WGMn3:2: Waveform Generation Mode
See TCCRnA register description.
• Bit 2:0 - CSn2:0: Clock Select
The three clock select bits select the clock source to be used by the Timer/Counter, see
Figure 54 and Figure 55.
If external pin modes are used for the Timer/Countern, transitions on the Tn pin will
clock the counter even if the pin is configured as an output. This feature allows software
control of the counting.
Timer/Counter 1 Control
Register C – TCCR1C
Table 62. Clock Select Bit Description
CSn2 CSn1 CSn0 Description
0 0 0 No clock source. (Timer/counter stopped)
0 0 1 clk
I/O
/1 (No prescaling
0 1 0 clk
I/O
/8 (From prescaler)
0 1 1 clk
I/O
/64 (From prescaler)
1 0 0 clk
I/O
/256 (From prescaler)
1 0 1 clk
I/O
/1024 (From prescaler)
1 1 0 External clock source on Tn pin. Clock on falling edge
1 1 1 External clock source on Tn pin. Clock on rising edge
Bit 7 6 5 4 3 2 1 0
FOC1A FOC1B FOC1C – – – – – TCCR1C
Read/Write W W W R R R R R
Initial value 0 0 0 0 0 0 0 0