Reading the pin value, Atmega162/v – Rainbow Electronics ATmega162V User Manual
Page 64
64
ATmega162/V
2513E–AVR–09/03
enabled state is fully acceptable, as a high-impedant environment will not notice the dif-
ference between a strong high driver and a pull-up. If this is not the case, the PUD bit in
the SFIOR Register can be set to disable all pull-ups in all ports.
Switching between input with pull-up and output low generates the same problem. The
user must use either the tri-state ({DDxn, PORTxn} = 0b00) or the output high state
({DDxn, PORTxn} = 0b11) as an intermediate step.
Table 27 summarizes the control signals for the pin value.
Reading the Pin Value
Independent of the setting of Data Direction bit DDxn, the port pin can be read through
the PINxn Register bit. As shown in Figure 29, the PINxn Register bit and the preceding
latch constitute a synchronizer. This is needed to avoid metastability if the physical pin
changes value near the edge of the internal clock, but it also introduces a delay. Figure
30 shows a timing diagram of the synchronization when reading an externally applied
pin value. The maximum and minimum propagation delays are denoted t
pd,max
and t
pd,min
respectively.
Figure 30. Synchronization when Reading an Externally Applied Pin Value
Table 27. Port Pin Configurations
DDxn
PORTxn
PUD
(in SFIOR)
I/O
Pull-up
Comment
0
0
X
Input
No
Tri-state (Hi-Z)
0
1
0
Input
Yes
Pxn will source current if ext. pulled
low.
0
1
1
Input
No
Tri-state (Hi-Z)
1
0
X
Output
No
Output Low (Sink)
1
1
X
Output
No
Output High (Source)
XXX
in r17, PINx
0x00
0xFF
INSTRUCTIONS
SYNC LATCH
PINxn
r17
XXX
SYSTEM CLK
t
pd, max
t
pd, min