Atmega162/v – Rainbow Electronics ATmega162V User Manual
Page 53
53
ATmega162/V
2513E–AVR–09/03
if the WDCE bit has logic level one. To disable an enabled Watchdog Timer, the follow-
ing procedure must be followed:
1.
In the same operation, write a logic one to WDCE and WDE. A logic one must be
written to WDE even though it is set to one before the disable operation starts.
2.
Within the next four clock cycles, write a logic 0 to WDE. This disables the
Watchdog.
In safety level 2, it is not possible to disable the Watchdog Timer, even with the algo-
rithm described above. See “Timed Sequences for Changing the Configuration of the
Watchdog Timer” on page 55.
• Bits 2..0 – WDP2, WDP1, WDP0: Watchdog Timer Prescaler 2, 1, and 0
The WDP2, WDP1, and WDP0 bits determine the Watchdog Timer prescaling when the
Watchdog Timer is enabled. The different prescaling values and their corresponding
Timeout Periods are shown in Table 23.
Table 23. Watchdog Timer Prescale Select
WDP2
WDP1
WDP0
Number of WDT
Oscillator Cycles
Typical Time-out
at V
CC
= 3.0V
Typical Time-out
at V
CC
= 5.0V
0
0
0
16K (16,384)
17 ms
16 ms
0
0
1
32K (32,768)
34 ms
33 ms
0
1
0
65K (65,536)
69 ms
65 ms
0
1
1
128K (131,072)
0.14 s
0.13 s
1
0
0
256K (262,144)
0.27 s
0.26 s
1
0
1
512K (524,288)
0.55 s
0.52 s
1
1
0
1,024K (1,048,576)
1.1 s
1.0 s
1
1
1
2,048K (2,097,152)
2.2 s
2.1 s