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Timer/counter1 – tcnt1h and tcnt1l, Timer/counter3 – tcnt3h and tcnt3l, Output compare register 1 a – ocr1ah and ocr1al – Rainbow Electronics ATmega162V User Manual

Page 132: Output compare register 1 b – ocr1bh and ocr1bl, Output compare register 3 a – ocr3ah and ocr3al, Output compare register 3 b – ocr3bh and ocr3bl, Atmega162/v

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132

ATmega162/V

2513E–AVR–09/03

Timer/Counter1 – TCNT1H
and TCNT1L

Timer/Counter3 – TCNT3H
and TCNT3L

The two Timer/Counter I/O locations (TCNTnH and TCNTnL, combined TCNTn) give
direct access, both for read and for write operations, to the Timer/Counter unit 16-bit
counter. To ensure that both the high and low bytes are read and written simultaneously
when the CPU accesses these registers, the access is performed using an 8-bit tempo-
rary high byte register (TEMP). This temporary register is shared by all the other 16-bit
registers. See “Accessing 16-bit Registers” on page 108.

Modifying the counter (TCNTn) while the counter is running introduces a risk of missing
a Compare Match between TCNTn and one of the OCRnx Registers.

Writing to the TCNTn Register blocks (removes) the Compare Match on the following
timer clock for all compare units.

Output Compare Register 1 A
– OCR1AH and OCR1AL

Output Compare Register 1 B
– OCR1BH and OCR1BL

Output Compare Register 3 A
– OCR3AH and OCR3AL

Output Compare Register 3 B
– OCR3BH and OCR3BL

Bit

7

6

5

4

3

2

1

0

TCNT1[15:8]

TCNT1H

TCNT1[7:0]

TCNT1L

Read/Write

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

Initial Value

0

0

0

0

0

0

0

0

Bit

7

6

5

4

3

2

1

0

TCNT3[15:8]

TCNT3H

TCNT3[7:0]

TCNT3L

Read/Write

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

Initial Value

0

0

0

0

0

0

0

0

Bit

7

6

5

4

3

2

1

0

OCR1A[15:8]

OCR1AH

OCR1A[7:0]

OCR1AL

Read/Write

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

Initial Value

0

0

0

0

0

0

0

0

Bit

7

6

5

4

3

2

1

0

OCR1B[15:8]

OCR1BH

OCR1B[7:0]

OCR1BL

Read/Write

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

Initial Value

0

0

0

0

0

0

0

0

Bit

7

6

5

4

3

2

1

0

OCR3A[15:8]

OCR3AH

OCR3A[7:0]

OCR3AL

Read/Write

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

Initial Value

0

0

0

0

0

0

0

0

Bit

7

6

5

4

3

2

1

0

OCR3B[15:8]

OCR3BH

OCR3B[7:0]

OCR3BL

Read/Write

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

Initial Value

0

0

0

0

0

0

0

0