Rainbow Electronics ATmega162V - Manual (Page 124)

124
ATmega162/V
2513E–AVR–09/03
than any of the compare registers, a Compare Match will never occur between the
TCNTn and the OCRnx.
As Figure 54 shows the output generated is, in contrast to the phase correct mode, sym-
metrical in all periods. Since the OCRnx Registers are updated at BOTTOM, the length
of the rising and the falling slopes will always be equal. This gives symmetrical output
pulses and is therefore frequency correct.
Using the ICRn Register for defining TOP works well when using fixed TOP values. By
using ICRn, the OCRnA Register is free to be used for generating a PWM output on
OCnA. However, if the base PWM frequency is actively changed by changing the TOP
value, using the OCRnA as TOP is clearly a better choice due to its double buffer
feature.
In phase and frequency correct PWM mode, the compare units allow generation of
PWM waveforms on the OCnx pins. Setting the COMnx1:0 bits to two will produce a
non-inverted PWM and an inverted PWM output can be generated by setting the
COMnx1:0 to three (See Table 55 on page 128). The actual OCnx value will only be vis-
ible on the port pin if the data direction for the port pin is set as output (DDR_OCnx). The
PWM waveform is generated by setting (or clearing) the OCnx Register at the Compare
Match between OCRnx and TCNTn when the counter increments, and clearing (or set-
ting) the OCnx Register at Compare Match between OCRnx and TCNTn when the
counter decrements. The PWM frequency for the output when using phase and fre-
quency correct PWM can be calculated by the following equation:
The N variable represents the prescaler divider (1, 8, 64, 256, or 1024). For
Timer/Counter3 also prescaler factors 16 and 32 are available.
The extreme values for the OCRnx Register represents special cases when generating
a PWM waveform output in the phase correct PWM mode. If the OCRnx is set equal to
BOTTOM the output will be continuously low and if set equal to TOP the output will be
set to high for non-inverted PWM mode. For inverted PWM the output will have the
opposite logic values. If OCRnA is used to define the TOP value (WGMn3:0 = 9) and
COMnA1:0 = 1, the OCnA output will toggle with a 50% duty cycle.
f
OC nxP FCP WM
f
clk_I/O
2 N TOP
⋅ ⋅
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