Data modes, Figure 73, D figure 74 f – Rainbow Electronics ATmega162V User Manual

Page 164: Figure 74 fo, Atmega162/v

164

ATmega162/V

2513E–AVR–09/03

Data Modes

There are four combinations of SCK phase and polarity with respect to serial data,
which are determined by control bits CPHA and CPOL. The SPI data transfer formats
are shown in Figure 73 and Figure 74. Data bits are shifted out and latched in on oppo-
site edges of the SCK signal, ensuring sufficient time for data signals to stabilize. This is
clearly seen by summarizing Table 66 and Table 67, as done below:

Figure 73. SPI Transfer Format with CPHA = 0

Figure 74. SPI Transfer Format with CPHA = 1

Table 69. CPOL and CPHA Functionality

Leading Edge

Trailing Edge

SPI Mode

CPOL=0, CPHA=0

Sample (Rising)

Setup (Falling)

CPOL=0, CPHA=1

Setup (Rising)

Sample (Falling)

CPOL=1, CPHA=0

Sample (Falling)

Setup (Rising)

CPOL=1, CPHA=1

Setup (Falling)

Sample (Rising)

Bit 1
Bit 6

LSB
MSB

SCK (CPOL = 0)
mode 0

SAMPLE I
MOSI/MISO

CHANGE 0
MOSI PIN

CHANGE 0
MISO PIN

SCK (CPOL = 1)
mode 2

MSB
LSB

Bit 6
Bit 1

Bit 5
Bit 2

Bit 4
Bit 3

Bit 3
Bit 4

Bit 2
Bit 5

MSB first (DORD = 0)
LSB first (DORD = 1)

SCK (CPOL = 0)
mode 1