Rainbow Electronics ATmega162V - Manual (Page 30)

30
ATmega162/V
2513E–AVR–09/03
Special Function IO Register –
SFIOR
• Bit 6 – XMBK: External Memory Bus Keeper Enable
Writing XMBK to one enables the Bus Keeper on the AD7:0 lines. When the Bus Keeper
is enabled, AD7:0 will keep the last driven value on the lines even if the XMEM interface
has tri-stated the lines. Writing XMBK to zero disables the Bus Keeper. XMBK is not
qualified with SRE, so even if the XMEM interface is disabled, the bus keepers are still
activated as long as XMBK is one.
• Bit 6..3 – XMM2, XMM1, XMM0: External Memory High Mask
When the External Memory is enabled, all Port C pins are used for the high address
byte by default. If the full 60KB address space is not required to access the external
memory, some, or all, Port C pins can be released for normal Port Pin function as
described in Table 4. As described in “Using all 64KB Locations of External Memory” on
page 32, it is possible to use the XMMn bits to access all 64KB locations of the external
memory.
Using all Locations of
External Memory Smaller than
64 KB Since the external memory is mapped after the internal memory as shown in Figure 11,
the external memory is not addressed when addressing the first 1,280 bytes of data
space. It may appear that the first 1,280 bytes of the external memory are inaccessible
(external memory addresses 0x0000 to 0x04FF). However, when connecting an exter-
nal memory smaller than 64 KB, for example 32 KB, these locations are easily accessed
simply by addressing from address 0x8000 to 0x84FF. Since the External Memory
Address bit A15 is not connected to the external memory, addresses 0x8000 to 0x84FF
will appear as addresses 0x0000 to 0x04FF for the external memory. Addressing above
address 0x84FF is not recommended, since this will address an external memory loca-
tion that is already accessed by another (lower) address. To the Application software,
the external 32 KB memory will appear as one linear 32 KB address space from 0x0500
to 0x84FF. This is illustrated in Figure 17. Memory configuration B refers to the
ATmega161 compatibility mode, configuration A to the non-compatible mode.
Bit 7 6 5 4 3 2 1 0
TSM XMBK XMM2 XMM1 XMM0 PUD PSR2 PSR310 SFIOR
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value 0 0 0 0 0 0 0 0
Table 4. Port C Pins Released as Normal Port Pins when the External Memory is
Enabled
XMM2 XMM1 XMM0 # Bits for External Memory Address Released Port Pins
0 0 0 8 (Full 60 KB space) None
0 0 1 7 PC7
0 1 0 6 PC7 - PC6
0 1 1 5 PC7 - PC5
1 0 0 4 PC7 - PC4
1 0 1 3 PC7 - PC3
1 1 0 2 PC7 - PC2
1 1 1 No Address high bits Full Port C