Rainbow Electronics ATmega103L - Manual (Page 85)

ATmega603/103
85
Port D Schematics
Note that all port pins are synchronized. The synchronization latches are however, not shown in the figures.
Figure 62. Port D Schematic Diagram (Pins PD0, PD1, PD2 and PD3)
Figure 63. Port D Schematic Diagram (Pin PD4)
DA
T
A
B
U
S
D
D
Q
Q
RESET
RESET
C
C
WD
WP
RD
MOS
PULL-
UP
PDn
R
R
WP:
WD:
RL:
RP:
RD:
n: WRITE PORTD
WRITE DDRD
READ PORTD LATCH
READ PORTD PIN
READ DDRD
0, 1, 2, 3
DDDn
PORTDn
INTn
RL
RP
DA
T
A
B
U
S
D
D
Q
Q
RESET
RESET
C
C
WD
WP
RD
MOS
PULL-
UP
PD4
R
R
WP:
WD:
RL:
RP:
RD:
ACIC:
ACO: WRITE PORTD
WRITE DDRD
READ PORTD LATCH
READ PORTD PIN
READ DDRD
COMPARATOR IC ENABLE
COMPARATOR OUTPUT
DDD4
PORTD4
NOISE CANCELER EDGE SELECT ICF1
ICNC1 ICES1
0
1
ACIC
ACO
RL
RP