Rainbow Electronics ATmega103L - Manual (Page 18)

ATmega603/103
18
Figure 21. Single Cycle ALU Operation
The internal data SRAM access is performed in two System Clock cycles as described in Figure 22.
Figure 22. On-Chip Data SRAM Access Cycles
See “Interface to external SRAM” on page 72 for a description of the access to the external SRAM.
System Clock Ø
Total Execution Time
Register Operands Fetch
ALU Operation Execute
Result Write Back
T1 T2 T3 T4
System Clock Ø
WR
RD
Data
Data
Address Address
T1 T2 T3 T4
Prev. Address
Read
Wr
ite