Rainbow Electronics ATmega103L - Manual (Page 42)

ATmega603/103
42
• Bit 1 - OCR0UB: Output Compare Register0 Update Busy
When Timer/Counter0 operates asynchronously and OCR0 is written, this bit becomes set (one). When OCR0 has been
updated from the temporary storage register, this bit is cleared (zero) by hardware. A logical zero in this bit indicates that
OCR0 is ready to be updated with a new value.
•
Bit 0 - TCR0UB: Timer/Counter Control Register0 Update Busy
When Timer/Counter0 operates asynchronously and TCCR0 is written, this bit becomes set (one). When TCCR0 has been
updated from the temporary storage register, this bit is cleared (zero) by hardware. A logical zero in this bit indicates that
TCCR0 is ready to be updated with a new value.
If a write is performed to any of the three Timer/Counter0 registers while its update busy flag is set (one), the updated value
might get corrupted and cause an unintentional interrupt to occur.
When reading TCNT0, OCR0 and TCCR0, there is a difference in result. When reading TCNT0, the actual timer value is
read. When reading OCR0 or TCCR0, the value in the temporary storage register is read.
Asynchronous Operation of Timer/Counter0
When Timer/Counter0 operates synchronously, all operations and timing are identical to Timer/Counter2. During asynchro-
nous operation, however, some considerations must be taken.
• WARNING: When switching between asynchronous and synchronous clocking of Timer/Counter0, the timer registers,
TCNT0, OCR0 and TCCR0 might get corrupted. Safe procedure for switching clock source:
1. Disable the timer 0 interrupts OCIE0 and TOIE0.
2. Select clock source by setting ASO as appropriate.
3. Write new values to TCNT0, OCR0 and TCCR0.
4. If switching to asynchronous operation: Wait for TCNT0UB, OCR0UB and TCR0UB to be cleared.
5. Enable interrupts if needed.
• The oscillator is optimized for use with a 32,768Hz watch crystal. An external clock signal applied to this pin goes
through the same amplifier having a bandwidth of 256kHz. The external clock signal should therefore be in the interval
0Hz - 256kHz. The frequency of the clock signal applied to the TOSC1 pin must be lower than one fourth of the CPU
main clock frequency. Observe that CPU clock frequency can be lower than the XTAL frequency if the XTAL divider is
enabled.
• When writing to one of the registers TCNT0, OCR0, or TCCR0, the value is transferred to a temporary register, and
latched after two positive edges on TOSC1. The user should not write a new value before the contents of the temporary
register have been transferred to its destination. Each of the three mentioned registers have their individual temporary
register, which means that e.g. writing to TCNT0 does not disturb an OCR0 write in progress. To detect that a transfer to
the destination register has taken place, a Asynchronous Status Register - ASSR has been implemented.
• When entering Power Save mode after having written to TCNT0, OCR0 or TCCR0, the user must wait until the written
register has been updated if Timer/Counter0 is used to wake up the device. Otherwise, the MCU will go to sleep before
the changes have had any effect. This is extremely important if the output compare0 interrupt is used to wake up the
device; Output compare is disabled during write to OCR0 or TCNT0. If the write cycle is not finished (i.e. the user goes to
sleep before the OCR0UB bit returns to zero), the device will never get a compare match and the MCU will not wake up.
• If Timer/Counter0 is used to wake up the device from Power Save mode, precautions must be taken if the user wants to
re-enter Power Save mode; The interrupt logic needs one TOSC1 cycle to get reset. If the time between wake up and re-
entering Power Save mode is less than one TOSC1 cycle, the interrupt will not occur and the device will fail to wake up. If
the user is in doubt whether the time before re-entering Power Save is sufficient, the following algorithm can be used to
ensure that one TOSC1 cycle has elapsed:
1. Write a value to TCCR0, TCNT0 or OCR0
2. Wait until the corresponding Update Busy flag in ASSR returns to zero.
3. Enter Power Save mode
• When asynchronous operation is selected, the 32 kHz oscillator for Timer/Counter0 is always running, except in power
down mode. After a power up reset or wake-up from power down, the user should be aware of the fact that this oscillator
might take as long as one second to stabilize. Therefore, the content of all Timer/Counter0 registers must be considered