Rainbow Electronics ATmega103L - Manual (Page 75)

ATmega603/103
75
Port A Data Register - PORTA
Port A Data Direction Register - DDRA
Port A Input Pins Address - PINA
The Port A Input Pins address - PINA - is not a register, and this address enables access to the physical value on each Port
A pin. When reading PORTA the Port A Data Latch is read, and when reading PINA, the logical values present on the pins
are read.
Port A as General Digital I/O
All 8 pins in Port A have equal functionality when used as digital I/O pins.
PAn, General I/O pin: The DDAn bit in the DDRA register selects the direction of this pin, if DDAn is set (one), PAn is con-
figured as an output pin. If DDAn is cleared (zero), PAn is configured as an input pin. If PORTAn is set (one) when the pin
configured as an input pin, the MOS pull up resistor is activated. To switch the pull up resistor off, PORTAn has to be
cleared (zero) or the pin has to be configured as an output pin. The port pins are tri-stated when a reset condition becomes
active, even if the clock is not running.
Note: n: 7,6...0, pin number
Port A Schematics
Note that all port pins are synchronized. The synchronization latch is however, not shown in the figure.
Bit 7 6 5 4 3 2 1 0
$1B ($3B) PORTA7 PORTA6 PORTA5 PORTA4 PORTA3 PORTA2 PORTA1 PORTA0 PORTA
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial value 0 0 0 0 0 0 0 0
Bit 7 6 5 4 3 2 1 0
$1A ($3A) DDA7 DDA6 DDA5 DDA4 DDA3 DDA2 DDA1 DDA0 DDRA
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial value 0 0 0 0 0 0 0 0
Bit 7 6 5 4 3 2 1 0
$19 ($39) PINA7 PINA6 PINA5 PINA4 PINA3 PINA2 PINA1 PINA0 PINA
Read/Write R R R R R R R R
Initial value Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z
Table 29. DDAn Effects on Port A Pins
DDAn PORTAn I/O Pull up Comment
0 0 Input No Tri-state (Hi-Z)
0 1 Input Yes PAn will source current if ext. pulled low.
1 0 Output No Push-Pull Zero Output
1 1 Output No Push-Pull One Output